In current microelectronics fabrication technology, a variety of techniques are employed to create multilayered structures having specific electron-transport configurations in both the horizontal direction and the vertical direction. The object of these fabrication techniques is the precise formation of electronically active circuits on the molecular level. Some processing techniques commonly used to achieve these structures are wet processing and plasma etching. These techniques are utilized to selectively expose and to mask conductive regions so that the multilayered structure can be appropriately built in the vertical direction, with the desired horizontal base region. These types of lithographic processes, however, have process limitations which directly affect the design of the circuitry which can be accomplished, as well as the overall yield of any fabrication processes which use these lithographic techniques. In light of these process limitations, there is ample motivation for the development of processes for selectively exposing and covering regions on the multilayered structure which are more selective and have higher yields than existing lithographic processing techniques.
The present invention provides greater etching specificity than prior lithographic techniques because it involves molecular-level interaction wherein selective etching can be accomplished without need for masking adjoining regions. The present invention has the ability to process different layers of the multilayer device simultaneously. The present invention takes advantage of a unique physical property of the materials to be processed to create localized reactive conditions without the need for additional thermal energy, or the need to externally generate free electrons to create a working plasma. The present invention is able to achieve these goals by selectively providing free electrons from conductive materials using a tunable radiation source whose energy can be adjusted to excite the electrons of one material preferentially to an adjacent material. This recognition enables the present invention to be used in a variety of common semiconductor processing steps with enhanced selectivity, and with fewer process steps, leading to more precise circuit design capability and higher fabrication yields.